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Key words: code generation, high-level synthesis, instruction set constraints
Due to an increasing need for flexibility, embedded systems embody more and more programmable processors as their core components. Because of silicon area and power considerations, the corresponding instruction sets are often highly encoded to minimize code size for given performance requirements. This has hampered the development of robust optimizing compilers because the resulting irregular instruction set architectures are far from convenient compiler targets. Among others, they introduce a strong phase coupling between the tasks of instruction selection and scheduling. Traditional methods perform these tasks in different phases, thereby yielding inferior schedules. In this paper, we present an approach that reduces the need for explicit instruction selection by transferring constraints implied by the instruction set to static resource constraints. All resulting schedules are then guaranteed to correspond to a valid implementation with available instructions. We demonstrate a practical way to identify and construct a static resource model from a given instruction set. Experimental results show the efficacy of our approach.
(postscript / pdf version of the complete paper)
Note that the paper is superseded by the following publication:
Q. Zhao, B. Mesman, and T. Basten. Static Resource Models for Code-Size Efficient Embedded Processors. ACM Transacions on Embedded Computing Systems, 2(2):219-250, May 2003. ACM Press. (abstract / postscript / pdf) © ACM.
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