Task-level Timing Models for Guaranteed Performance in Multiprocessor Networks-on-Chip

Key words: system-on-chip, network-on-chip, real-time, data flow graph, performance evaluation, buffer minimization

We consider a dynamic application running on a multiprocessor network-on-chip as a set of independent jobs, each job possibly running on multiple processors. To provide guaranteed quality and performance, the scheduling of jobs, jobs themselves and the hardware must be amenable to timing analysis. For a certain class of applications and multiprocessor architectures, we propose exact timing models that effectively co-model both the computation and communication of a job. The models are based on interprocessor communication (IPC) graphs [1]. Our main contribution is a precise model of network-on-chip communication, including buffer models. We use a JPEG-decoder job as an example to demonstrate that our models can be used in practice to derive upper bounds on the job execution time and to reason about optimal buffer sizes.

1. Bambha, N., Kianzad, V., Khandelia, M., and Bhattacharrya, S.S., Intermediate Representations for Design Automation of Multiprocessor DSP Systems. In Design Automation for Embedded Systems, vol. 7, 307-323, Kluwer Academic Publishers, 2002.

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